`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:32:10 04/05/2011 
// Design Name: 
// Module Name:    IFtoID_Buffer 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module IFtoID_Buffer(clk, pcIn, instrIn, pcOut, instrOut);
	input clk;
	input [15:0] pcIn;
	input [15:0] instrIn;
	output [15:0] pcOut;
	output [15:0] instrOut;

	reg [15:0] pcOut;
	reg [15:0] instrOut;
	
	always @ (posedge clk)
	begin
		pcOut <= pcIn;
		instrOut <= instrIn;
	end
endmodule
